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for further information contact your local stmicroelectronics sales office. august 2014 docid026791 rev 1 1/19 STEVAL-IME008V1 evaluation board based on the sthv749 high voltage pulser data brief features ? 4-channel outputs: high voltage and low voltage bnc connectors ? load simulator using signal equivalent circuits ? possibility to set up own load simulator ? 16 preset waveforms ? usb connector to connect stm32 with pc and supply power to it ? 4 mb serial flash memory to host fpga code and waveforms ? memory expansion connector to add external serial flash ? connectors to supply high voltage and low voltage to the sthv749 output stage ? leds to monitor the power management stage ? human machine interface to select, start and stop the generation of the preset waveforms ? 25 leds to monitor board behavior ? rohs compliant description the STEVAL-IME008V1 is a product evaluation board designed around the sthv749 4-channel 7-level high voltage pulser, a state-of-the-art device designed for ultrasound imaging applications. the output waveforms can be displayed directly on an oscilloscope by connecting the scope probe to the relative bncs. 16 preset waveforms are available to test the hv pulser under varying conditions. www.st.com
schematic diagrams STEVAL-IME008V1 2/19 docid026791 rev 1 1 schematic diagrams figure 1. STEVAL-IME008V1 circuit schematic (1 of 16) dataout0 dataout1 dataout2 dataout3 dataout4 dataout5 dataout6 dataout7 dataout8 dataout9 dataout10 dataout11 dataout[0:15] mcu_fpga_gpio[0:7] dataout12 dataout13 hvpcw dvdd vddp hvp0 hvmcw vddm hvm0 dvdd vddp vddm hvp0 hvp1 hvpcw hvm0 hvm1 hvmcw hvm1 hvp1 fpga_blk fpga thsd_en fpga_spi_cclk fpga_spi_mosi fpga_spi_miso1 fpga_spi_miso2 fpga_spi_miso3 fpga_spi_sel +vfpga_core_1v2 +vfpga_io_3v3 dataout[0:15] cw ck mcu_fpga_gpio[0:7] mcu_fpga_prog mcu_fpga_init_b mcu_fpga_mode1 fpga_mcu_done mcu_fpga_osc_en fpga_mcu_awake mcu_fpga_suspend board_power_blk board_power hvp0 dvdd vddp vddm hvm0 +vfpga_core_1v2 +vfpga_io_3v3 flash_3v3 usb_disconnect usb_dm usb_dp mcu_3v3 hvpcw hvmcw hvp1 hvm1 stm32_flash_blk stm32_flash flash_c flash_dq0 flash_ns flash_dq2 flash_dq3 flash_dq1 usb_disconnect usb_dm usb_dp mcu_fpga_prog mcu_fpga_init_b mcu_fpga_mode1 fpga_mcu_done mcu_fpga_osc_en fpga_mcu_awake mcu_fpga_suspend flash_3v3 mcu_3v3 fpga_gpio[0:7] sthv749_blk sthv749 dvdd vddp vddm in1_0 in1_1 in4_0 in3_1 in4_1 cw thsd_en ck in2_0 in3_0 in2_1 hvm_cw hvp_cw hvp1 in2_2 in3_2 hvm0 in4_2 hvm1 in1_2 hvp0 sel gspg30072014di1135
docid026791 rev 1 3/19 STEVAL-IME008V1 schematic diagrams 19 figure 2. STEVAL-IME008V1 circuit schematic (2 of 16) sot23-5l c7 details: digikey (445-4998-2-nd) - tdk (c1005x5r0j105k) package 0402 usb c8 details: digikey (478-2552-2-nd) - avx (tacl225m006xta) package 0603 sott323-6l rs (515-1995) molex (54819-0572) kingbright kp2012surc rs: 466-3829 farnell: 8529930 led 0805 usb on dm dp dp dm usbdp usbdm usb_disconnect usb_disconnect usbdm usbdp usb_3v3 usb_disconnect usb_dm usb_dp usb_5v usb_5v c3 4.7nf c8 2.2uf 6.3v r90 56r cn1 1 usb_minib vbus dm 2 dp 3 4 id nc 5 gnd 6 shell 7 shell 8 shell 9 shell d26 red u1 d1 1 d2 d3 usbuf02w6 grd 2 3 4 5 3.3v d4 6 c11 33nf r1 1m c7 1uf u2 vin 1 lds3985m33r gnd 2 3 inh 4 byps 5 vout gspg30072014di1140
schematic diagrams STEVAL-IME008V1 4/19 docid026791 rev 1 figure 3. STEVAL-IME008V1 circuit schematic (3 of 16) 3.3v power management j4 details phoenix contact (mfg code mpt 0.5/2-2.54) rs (220-4260) c12 and c13 detail tdk (c1608x5r0j475k) - digikey (445-5178-2-nd) dimension 0603 - eia 1608 c14 detail tdk (c2012x7r1a106k) - digikey (445-6857-2-nd) dimension 0805 - eia 2012 l1 detail tdk (vlf4012at-2r2m1r5) - rs (614-3147) not assembly mcu fpga 3v3 connector 3v3 sw1 details: sw1 rs 711-8329 knitter-switch (mms228t) usb_3v3 ext_3v3 mcu_3v3 +vfpga_io_3v3 +vfpga_core_1v2 flash_3v3 flash_3v3 ext_3v3 dvdd d27 red j4 1 2 l1 2.2uh c12 4u7 6.3v mms228t 2 com_1a 7 com_1b 3 on_2a 6 on_2b 1 on_1a 8 on_1b nc 4 nc 5 u3 st1s12xx vin 4 5 fb/vo en 1 2 gnd sw 3 c13 4u7 6.3v r124 56 c14 10u 10v r125 56 j41 1 2 d28 red d1 sm2t3v3a gspg30072014di1150
docid026791 rev 1 5/19 STEVAL-IME008V1 schematic diagrams 19 figure 4. STEVAL-IME008V1 circuit schematic (4 of 16) sthv800 power management mkds 1.5/2-5.08) j2 details rs 2x(193-0564) phoenix contact (mfg code c1, c2, c9, c10, c15, c16 details: gnd_power digikey (445-5217-2-nd) - tdk (ckg57nx7s2a226m) package 6.5mm x 5.5 mm c4, c5, c6 details: digikey (445-1436-2-nd) - tdk (c3225x5r1c226m) package 1210 - eia 3225 dvdd vddp gnd hvpcw hvp1 hvp0 gnd vddm hvmcw hvm1 hvm0 gnd low power - high voltage + high voltage j1 details rs 2x(193-0564) phoenix contact (mfg code mkds 1.5/2-5.08) j3 details rs 2x(193-0564) phoenix contact (mfg code hvpcw hvp0 dvdd vddp vddm hvp1 hvmcw hvm0 hvm1 hvpcw hvp0 dvdd vddp vddm hvmcw hvm0 hvp1 hvm1 gnd_power mkds 1.5/2-5.08) gnd_power gnd_power gnd_shield r2 0 c9 100v 22000n 100v 0 r123 c2 100v 22000n 100v j2 lv 1 2 3 4 c4 16v 22000n 16v c79 100v 22000n 100v c6 16v 22000n 16v c78 100v 22000n 100v c10 100v 22000n 100v c5 16v 22000n 16v 22000n 100v c1 100v j3 hvm 1 2 3 4 j1 hvp 1 2 3 4 gspg30072014di1155
schematic diagrams STEVAL-IME008V1 6/19 docid026791 rev 1 figure 5. STEVAL-IME008V1 circuit schematic (5 of 16) jumper j5 is used to control i/o pullups during fpga configuration. diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair open (default) to float i/o output during fpga configuration. set jumper 1:2 to enable i/o pullups during fpga configuration. diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair diff. pair c16 and c17 details: tdk (c2012x7r1a106k) - digikey (445-6857-2-nd) dimension 0805 - eia 2012 jumpers j35, j36 and j37 are used to set dataout output state. configure j35 and j36 to setup outputs idle state as follows: not assembly not assembly not assembly these jumpers hswapen open j37 (default) to connect fpga outputs close j37 to disconnect outputs (high-z) 00 - (j35 and j36 open) --> high-z (default) 01 - (j35 closed and j36 open) --> clamp/hvr_sw 11 - (j35 and j36 closed) --> high-z 10 - (j35 open and j36 closed) --> clamp idle state header 17x2 sthv748 i/o connector fpga disconnect dataout0 dataout1 dataout2 dataout3 dataout4 dataout5 dataout6 dataout7 dataout8 dataout9 dataout10 dataout11 dataout12 dataout13 dataout14 dataout15 dataout[0:15] hswapen ck thsd_en cw dataout11 thsd_en dataout0 dataout2 dataout4 dataout6 dataout8 dataout10 dataout12 dataout14 dataout1 dataout3 dataout5 dataout7 dataout9 dataout13 ck dataout15 cw hi_z idle_state1 idle_state0 thsd_en ck cw dataout[0:15] +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 r122 j5 10k 0402 jumper 1 2 c15 100n 0402 c16 10uf 10v 0805 j35 1 2 c17 10uf 10v 0805 j37 1 2 r120 10k 0402 u4a fpga - bank 0 xc6slx16-2csg324c c4 d4 a2 b2 c6 d6 a3 b3 a4 b4 a5 c5 e6 f7 a6 b6 e8 e7 a7 c7 c8 d8 f8 g8 a8 b8 c9 d9 a9 b9 c11 d11 a10 c10 f9 g9 a11 b11 f10 g11 a12 b12 e11 f11 c12 d12 a13 c13 e12 f12 a14 b14 e13 f13 a15 c15 c14 d14 a16 b16 r3 10k 0402 j6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 r121 10k 0402 c18 100n 0402 j36 12 io_0_l01n_vref io_0_l01p_hswapen io_0_l02n io_0_l02p io_0_l03n io_0_l03p io_0_l04n io_0_l04p io_0_l05n io_0_l05p io_0_l06n io_0_l06p io_0_l07n io_0_l07p io_0_l08n_vref io_0_l08p io_0_l09n io_0_l09p io_0_l10n io_0_l10p io_0_l11n io_0_l11p io_0_l32n io_0_l32p io_0_l33n io_0_l33p io_0_l34n_gclk18 io_0_l34p_gclk19 io_0_l35n_gclk16 io_0_l35p_gclk17 io_0_l36n_gclk14 io_0_l36p_gclk15 io_0_l37n_gclk12 io_0_l37p_gclk13 io_0_l38n_vref io_0_l38p io_0_l39n io_0_l39p io_0_l40n io_0_l40p io_0_l41n io_0_l41p io_0_l42n io_0_l42p io_0_l47n io_0_l47p io_0_l50n io_0_l50p io_0_l51n io_0_l51p io_0_l62n_vref io_0_l62p io_0_l63n_scp6 io_0_l63p_scp7 io_0_l64n_scp4 io_0_l64p_scp5 io_0_l65n_scp2 io_0_l65p_scp3 io_0_l66n_scp0 io_0_l66p_scp1 gspg30072014di1200
docid026791 rev 1 7/19 STEVAL-IME008V1 schematic diagrams 19 figure 6. STEVAL-IME008V1 circuit schematic (6 of 16) not assembly fpga user i/o stop_pb fpga_reset ctrl_led1 ctrl_led0 sel_prog_pb fpga_clk_66mhz start_pb fpga_dout_busy fpga_awake fpga_user_io_10 fpga_user_io_11 fpga_user_io_12 fpga_user_io_13 fpga_user_io_14 fpga_user_io_15 ctrl_led3 ctrl_led2 fpga_pmod1_p2 fpga_pmod1_p1 fpga_pmod1_p4 fpga_pmod1_p3 fpga_pmod1_p8 fpga_pmod1_p7 fpga_pmod1_p10 fpga_pmod1_p9 fpga_pmod2_p2 fpga_pmod2_p1 fpga_pmod2_p4 fpga_pmod2_p3 fpga_pmod2_p8 fpga_pmod2_p7 fpga_pmod2_p10 fpga_pmod2_p9 fpga_user_io_0 fpga_user_io_1 fpga_user_io_2 fpga_user_io_3 fpga_user_io_4 fpga_user_io_5 fpga_user_io_6 fpga_user_io_7 fpga_user_io_8 fpga_user_io_9 fpga_mcu_awake tp1 1 test point j7 header 16x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 u4b fpga - bank 1 xc6slx16-2csg324c f16 f15 c18 c17 g14 f14 d18 d17 g13 h12 e18 e16 k13 k12 f18 f17 h14 h13 h16 h15 g18 g16 k14 j13 l13 l12 k16 k15 l16 l15 h18 h17 j18 j16 k18 k17 l18 l17 m18 m16 n18 n17 p18 p17 n16 n15 t18 t17 u18 u17 n14 m14 m13 l14 p16 p15 io_1_l01n_a24_vref io_1_l01p_a25 io_1_l29n_a22_m1a14 io_1_l29p_a23_m1a13 io_1_l30n_a20_m1a11 io_1_l30p_a21_m1reset io_1_l31n_a18_m1a12 io_1_l31p_a19_m1cke io_1_l32n_a16_m1a9 io_1_l32p_a17_m1a8 io_1_l33n_a14_m1a4 io_1_l33p_a15_m1a10 io_1_l34n_a12_m1ba2 io_1_l34p_a13_m1we io_1_l35n_a10_m1a2 io_1_l35p_a11_m1a7 io_1_l36n_a8_m1ba1 io_1_l36p_a9_m1ba0 io_1_l37n_a6_m1a1 io_1_l37p_a7_m1a0 io_1_l38n_a4_m1clkn io_1_l38p_a5_m1clk io_1_l39n_m1odt io_1_l39p_m1a3 io_1_l40n_gclk10_m1a6 io_1_l40p_gclk11_m1a5 io_1_l41n_gclk8_m1casn io_1_l41p_gclk9_irdy1_m1rasn io_1_l42n_gclk6_trdy1_m1ldm io_1_l42p_gclk7_m1udm io_1_l43n_gclk4_m1dq5 io_1_l43p_gclk5_m1dq4 io_1_l44n_a2_m1dq7 io_1_l44p_a3_m1dq6 io_1_l45n_a0_m1ldqsn io_1_l45p_a1_m1ldqs io_1_l46n_foe_b_m1dq3 io_1_l46p_fcs_b_m1dq2 io_1_l47n_ldc_m1dq1 io_1_l47p_fwe_b_m1dq0 io_1_l48n_m1dq9 io_1_l48p_hdc_m1dq8 io_1_l49n_m1dq11 io_1_l49p_m1dq10 io_1_l50n_m1udqsn io_1_l50p_m1udqs io_1_l51n_m1dq13 io_1_l51p_m1dq12 io_1_l52n_m1dq15 io_1_l52p_m1dq14 io_1_l53n_vref io_1_l53p io_1_l61n io_1_l61p io_1_l74n_dout_busy io_1_l74p_awake gspg30072014di1205
schematic diagrams STEVAL-IME008V1 8/19 docid026791 rev 1 figure 7. STEVAL-IME008V1 circuit schematic (7 of 16) place r7 (1%) close to the clock source ds1088lu-66 device peripherral module (pmod) 66mhz external oscillator dx sx backup of u5 not assembly not assembly c26, c27, c30 and c31 detail tdk (c2012x7r1a106k) - digikey (445-6857-2-nd) dimension 0805 - eia 2012 pmod2 pmod1 66mhz osc when using backup oscillator x1, r126 have to be mounted and r6 must be unplaced. fpga_pmod1_p2 fpga_pmod1_p4 fpga_pmod1_p1 fpga_pmod1_p3 fpga_pmod1_p7 fpga_pmod1_p8 fpga_pmod1_p10 fpga_pmod1_p9 fpga_pmod2_p2 fpga_pmod2_p4 fpga_pmod2_p1 fpga_pmod2_p3 fpga_pmod2_p7 fpga_pmod2_p8 fpga_pmod2_p10 fpga_pmod2_p9 fpga_clk_66mhz mcu_fpga_osc_en mcu_fpga_osc_en +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 c28 100nf j9 header 6x2 2 4 6 8 10 12 1 3 5 7 9 11 x1 1 oe st gnd 2 4 vcc 3 out c25 100nf c27 10uf 10v 0805 c20 10nf c29 100nf c19 100nf c30 r6 10uf 10v 0805 10k nm c32 100nf r7 33r2 r126 10k c31 10uf 10v 0805 c26 10uf 10v 0805 u5 2 vcc ds1088lu-66 vcc 3 7 n/c n/c 8 1 out 4 gnd 5 gnd pdn 6 j8 header 6x2 2 4 6 8 10 12 1 3 5 7 9 11 two right-angle, 12-pin (2 x 6 female) peripheral module (pmod) headers (j8, j9) are interfaced to the fpga, with each header providing 3.3 v power, ground, and eight i/o's. these headers may be utilized as general-purpose i/os or may be used to interface to pmods. j6 and j8 are placed in close proximity (0'9" -centers) on the pcb in order to support dual pmods. gspg30072014di1210
docid026791 rev 1 9/19 STEVAL-IME008V1 schematic diagrams 19 figure 8. STEVAL-IME008V1 circuit schematic (8 of 16) sw2, sw3, sw4, details rs (378-6527) pushbuttons ctrl led green led kingbright kp2012surc rs: 466-3778 farnell: 8529906 led 0805 near start button near stop button idle state signal error signal program stop fpga reset start idle error red led kingbright kp2012surc rs: 466-3829 farnell: 8529930 led 0805 ctrl_led0 ctrl_led2 ctrl_led1 ctrl_led3 fpga_reset start_pb sel_prog_pb stop_pb +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 d3 green r10 56r 0402 r9 10k 0402 r12 56r 0402 sw3 r11 sw pushbutton-dpst 56r 0402 c22 100nf d4 green r5 10k 0402 c24 100nf r8 10k 0402 r4 10k 0402 sw2 sw pushbutton-dpst c21 100nf d2 green r13 56r 0402 d5 red sw4 sw pushbutton-dpst c23 100nf sw5 sw pushbutton-dpst gspg30072014di1215
schematic diagrams STEVAL-IME008V1 10/19 docid026791 rev 1 figure 9. STEVAL-IME008V1 circuit schematic (9 of 16) mcu_fpga_gpio2 mcu_fpga_gpio3 mcu_fpga_gpio0 mcu_fpga_gpio1 prog_led10 prog_led11 prog_led2 prog_led3 prog_led6 prog_led7 prog_led0 prog_led1 prog_led4 prog_led5 prog_led8 prog_led9 fpga_mode0 cclk fpga_spi_miso1 prog_led14 prog_led15 mcu_fpga_gpio6 mcu_fpga_gpio7 mcu_fpga_gpio4 mcu_fpga_gpio5 prog_led12 prog_led13 fpga_spi_miso2 fpga_spi_mosi fpga_spi_sel fpga_init_b fpga_spi_miso3 fpga_mode1 mcu_fpga_gpio[0:7] mcu_fpga_gpio0 mcu_fpga_gpio1 mcu_fpga_gpio2 mcu_fpga_gpio3 mcu_fpga_gpio4 mcu_fpga_gpio5 mcu_fpga_gpio6 mcu_fpga_gpio7 mcu_fpga_gpio[0:7] u4c fpga - bank 2 xc6slx16-2csg324c t15 r15 v16 u16 t13 r13 v15 u15 v14 t14 p12 n12 v13 u13 n11 m11 t11 r11 v12 t12 p11 n10 n9 m10 v11 u11 t10 r10 v10 u10 t8 r8 v9 t9 n8 m8 v8 u8 v7 u7 p8 n7 v6 t6 t7 r7 p7 n6 t5 r5 v5 u5 t3 r3 v4 t4 p6 n5 v3 u3 tp2 1 test point io_2_l01n_m0_cmpmiso io_2_l01p_cclk io_2_l02n_cmpmosi io_2_l02p_cmpclk io_2_l03n_mosi_csi_b_miso0 io_2_l03p_d0_din_miso_miso1 io_2_l05n io_2_l05p io_2_l12n_d2_miso3 io_2_l12p_d1_miso2 io_2_l13n_d10 io_2_l13p_m1 io_2_l14n_d12 io_2_l14p_d11 io_2_l15n io_2_l15p io_2_l16n_vref io_2_l16p io_2_l19n io_2_l19p io_2_l20n io_2_l20p io_2_l22n io_2_l22p io_2_l23n io_2_l23p io_2_l29n_gclk2 io_2_l29p_gclk3 io_2_l30n_gclk0_usercclk io_2_l30p_gclk1_d13 io_2_l31n_gclk30_d15 io_2_l31p_gclk31_d14 io_2_l32n_gclk28 io_2_l32p_gclk29 io_2_l40n io_2_l40p io_2_l41n_vref io_2_l41p io_2_l43n io_2_l43p io_2_l44n io_2_l44p io_2_l45n io_2_l45p io_2_l46n io_2_l46p io_2_l47n io_2_l47p io_2_l48n_rdwr_b_vref io_2_l48p_d7 io_2_l49n_d4 io_2_l49p_d3 io_2_l62n_d6 io_2_l62p_d5 io_2_l63n io_2_l63p io_2_l64n_d9 io_2_l64p_d8 io_2_l65n_cso_b io_2_l65p_init_b gspg30072014di1220
docid026791 rev 1 11/19 STEVAL-IME008V1 schematic diagrams 19 figure 10. STEVAL-IME008V1 circuit schematic (10 of 16) spi external programming header spi flash ctrl signals place r38 close to the fpga device fpga configuration configuration mode selection: fpga_mode0 = parallel (low) or serial (high) fpga_mode1 = master (low) or slave (high) to correct ext spi flash place d29 close to j10 c33 details: tdk (c2012x7r1a106k) - digikey (445-6857-2-nd) dimension 0805 - eia 2012 when fpga_init_b (bidirectional open-drain) is low the configuration memory is being cleared. when held low, the start of configuration is delayed. during configuration, a low on this output indicates that a configuration data error has occurred. cclk fpga_spi_miso1 fpga_spi_mosi fpga_spi_sel fpga_spi_miso2 fpga_mode0 fpga_init_b fpga_mode1 fpga_spi_miso3 mcu_fpga_init_b mcu_fpga_mode1 +vfpga_io_3v3 +vfpga_io_3v3 fpga_spi_cclk fpga_spi_miso1 fpga_spi_mosi fpga_spi_sel fpga_spi_miso2 fpga_spi_miso3 mcu_fpga_prog d29 green r22 2k43 0402 56 r127 r38 33r2 0402 r21 r18 2k43 0402 dnp j10 2k43 0402 dnp con10 10 1 2 3 4 5 6 7 8 9 c34 100nf r17 2k43 0402 r16 10k 0402 r39 na 0402 c33 10uf 10v 0805 r40 na 0402 gspg30072014di1230
schematic diagrams STEVAL-IME008V1 12/19 docid026791 rev 1 figure 11. STEVAL-IME008V1 circuit schematic (11 of 16) kingbright kp-3216syc rs: 466-3942 led 0805 program selector leds prog 0 prog 1 prog 2 prog 3 prog 4 prog 5 prog 6 prog 7 prog 8 prog 9 prog 10 prog 11 prog 12 prog 13 prog 14 prog 15 prog_led12 prog_led14 prog_led13 prog_led15 prog_led8 prog_led10 prog_led9 prog_led11 prog_led4 prog_led6 prog_led5 prog_led7 prog_led0 prog_led2 prog_led1 prog_led3 r24 68r 0402 d13 yellow d11 yellow d14 yellow r15 68r 0402 r19 68r 0402 r31 68r 0402 d15 yellow d18 yellow r34 68r 0402 r27 68r 0402 d6 yellow d21 yellow d12 yellow r23 68r 0402 d10 yellow r14 68r 0402 r28 68r 0402 d17 yellow r33 68r 0402 d20 yellow r32 68r 0402 d19 yellow r30 68r 0402 d9 yellow r25 68r 0402 d16 yellow r20 68r 0402 r26 68r 0402 r29 68r 0402 d7 yellow d8 yellow gspg30072014di1235
docid026791 rev 1 13/19 STEVAL-IME008V1 schematic diagrams 19 figure 12. STEVAL-IME008V1 circuit schematic (12 of 16) fpga bank 3 not used done program_b jumper j12 fpga into 1:2 to force mode. suspend mode. to control 2:3 (default) to allow mcu fpga suspend fpga jtag 0805 suspend & cmpcs_b 4-resistor array 3.2x1.6mm not assembly con14a xilinx parallel iv connector 2.0mm 7x2 shrouded header jumper j13 used to prevent fpga from programming from configuration source. set 1:2 to disable fpga programming. open (default) to enable fpga programming. c35, c40, c51, c58, c66 details murata (grm31cr60j107me39l) - digikey (490-4539-1-ndt ) dimension 1206 - eia 3216 near u3 near u6 to be placed to be placed resdip4x1206 not assembly not assembly suspend fpga prog disable done fpga jtag fpga prog not assembly not assembly not assembly not assembly xc6slx16-3csg324c c36, c37, c38, c41, c42, c52, c53, c59, c60, c67, c68 details dk (c1608x5r0j475k) - digikey (445-5178-2-nd) dimension 0603 - eia 1608 fpga_prog fpga_done fpga_prog fpga_suspend fpga_done fpga_cmp_cs_b fpga_tdi fpga_tms fpga_tck +vfpga_io_3v3 +vfpga_core_1v2 fpga_tdo mcu_fpga_prog fpga_mcu_done mcu_fpga_suspend +vfpga_io_3v3 +vfpga_core_1v2 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_core_1v2 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 +vfpga_io_3v3 r50 10k 0402 c36 c35 4.7uf 6.3v 0603 c64 100uf 6.3v 1206 c62 0.22uf 6.3v 0402 100nf r49 10k 0402 c63 c38 0.22uf 6.3v 0402 c61 4.7uf 6.3v 0603 r52 0.22uf 6.3v 0402 330 0402 c60 r48 4.7uf 6.3v 0603 10k 0402 r51 56r c56 0.22uf 6.3v 0402 d23 green c45 c55 0.22uf 6.3v 0402 c59 0.22uf 6.3v 0402 4.7uf 6.3v 0603 r44 49r 0402 c69 c53 0.22uf 6.3v 0402 0 r47 4.7uf 6.3v 0603 c48 c58 0.22uf 6.3v 0402 j12 100uf 6.3v 1206 header 3 1 2 3 c54 c43 0.22uf 6.3v 0402 c52 0.22uf 6.3v 0402 c42 4.7uf 6.3v 0603 r45 4.7uf 6.3v 0603 10k 0402 c71 0.22uf 6.3v 0402 q1 2n7002 c51 100uf 6.3v 1206 u6 1 74v1g32ctr 2 4 5 3 j13 jumper 1 2 c41 c47 4.7uf 6.3v 0603 c40 0.22uf 6.3v 0402 100uf 6.3v 1206 fpga - power & configuration tck a17 tms u4e xc6slx16-2csg324c b18 tdo d16 tdi d15 v2 program_b_2 r16 suspend done_2 v17 p13 cmpcs_b_2 vcco_0 b10 vcco_0 b15 b5 vcco_0 vcco_0 d13 d7 vcco_0 e10 vcco_0 vcco_1 e17 vcco_1 g15 vcco_1 j14 vcco_1 j17 vcco_1 m15 r17 vcco_1 p9 vcco_2 vcco_2 r12 r6 vcco_2 vcco_2 u14 u4 vcco_2 u9 vcco_2 e2 vcco_3 g4 vcco_3 j2 vcco_3 j5 vcco_3 m4 vcco_3 r2 vcco_3 b1 vccaux vccaux b17 vccaux e14 e5 vccaux e9 vccaux vccaux g10 vccaux j12 k7 vccaux m9 vccaux vccaux p10 vccaux p14 p5 vccaux g7 vccint vccint h11 h9 vccint vccint j10 j8 vccint vccint k11 k9 vccint vccint l10 l8 vccint vccint m12 m7 vccint gnd a18 gnd b13 gnd c3 gnd d10 gnd d5 gnd b7 gnd c16 gnd g17 gnd g2 gnd g5 gnd h10 gnd h8 gnd j11 gnd j15 gnd j4 gnd e15 gnd g12 gnd k8 gnd l11 gnd l9 gnd m17 gnd m2 gnd m6 gnd n13 gnd r1 gnd r14 gnd r18 gnd r4 gnd r9 gnd t16 gnd u12 gnd u6 gnd v1 gnd v18 gnd k10 gnd j9 gnd a1 rst1 c70 rs (378-6527) sw pushbutton-dpst j11 0.22uf 6.3v 0402 1 2 3 4 5 6 7 8 9 10 11 12 13 14 c68 r46 4.7uf 6.3v 0603 10k 0402 c67 c72 4.7uf 6.3v 0603 u7 0.22uf 6.3v 0402 4 2 74lx1g08ctr 1 5 3 c73 100nf c66 100uf 6.3v 1206 r41 49r 0402 c49 c65 0.22uf 6.3v 0402 0.22uf 6.3v 0402 rn1 resistor dip 4 1 2 3 4 8 7 6 5 r42 49r 0402 c44 c46 0.22uf 6.3v 0402 c57 0.22uf 6.3v 0402 0.22uf 6.3v 0402 r43 49r 0402 c50 c39 0.22uf 6.3v 0402 d22 0.22uf 6.3v 0402 stth102a c37 4.7uf 6.3v 0603 gspg30072014di1240
schematic diagrams STEVAL-IME008V1 14/19 docid026791 rev 1 figure 13. STEVAL-IME008V1 circuit schematic (13 of 16) c77, c80, c111, c112 details digikey (490-1462-2-nd) murata (grm188r72a271ka01d) j16, j17, j22, j23, j25, j26, j29 and j30 details tyco electronics (1-1337482-0) - rs (420-5401) sthv749 thsd xdcr_1 thsd j16, j17, j22, j23, j25, j26, j29 and j30 details tyco electronics (1-1337482-0) - rs (420-5401) xdcr_2 xdcr_3 xdcr_4 lvout_1 lvout_2 lvout_3 ck lvout_4 in1_0 d1, d2, d3 ,d4, d5, d6, d7, d8 diode dfls1200 rs-code 708-2324 in1_1 in2_0 in2_1 in3_0 in3_1 in4_0 in4_1 hvp0 hvp_cw dvdd vddp vddm hvm0 hvm_cw thsd_en dvdd thsd_en in5_0 in5_1 in6_0 in6_1 dvdd ck cw hvp0 hvm0 ck vddm hvp1 hvm1 hvm0 hvm1 in2_2 in2_1 in2_0 in1_2 in1_1 in1_0 cw in3_0 in3_1 in3_2 in4_0 in4_1 in4_2 sel vddp sel hvp0 hvm0 hvp1 w w c c _ _ m m v v h h hvp0 hvp_cw dvdd vddp vddm ck thsd_en in1_0 in1_1 cw in1_2 in2_0 in2_1 in2_2 in3_0 in3_1 in3_2 in4_0 in4_1 in4_2 hvp0 hvp_cw hvm0 hvm_cw hvp1 hvm1 sel b2s j17 1 2 c83 220n c76 20p 0805 d34 dfls1200 d33 dfls1200 c93 220n c90 220n r54 100 c85 220n r62 100 u8 sthv749 1 xdcr_1 2 xdcr_2 3 gnd_pwr 4 hvm0 5 hvm0 6 hvm0 7 hvm1 8 hvm1 9 hvm1 10 hvm_cw 11 xdcr_3 12 xdcr_4 13 gnd_pwr 14 lvout_3 15 lvout_4 16 gnd_pwr 17 in3_0 18 in3_1 19 in3_2 20 in4_0 21 in4_1 in4_2 22 thsd 23 vddp 24 vddp 25 agnd 26 vddm 27 hvp1 28 hvp1 29 hvp1 30 hvp0 31 hvp0 32 hvp0 33 in1_0 39 in1_1 40 in1_2 41 42 in2_0 43 in2_1 44 in2_2 45 gnd_pwr 46 lvout_1 47 lvout_2 48 gnd_pwr cw 38 34 hvp_cw dgnd 35 dvdd 36 ck 37 r55 100 tp3 1 test point cx2 220n cx10 220n cx11 220n c80 270p 100v 0603 cx3 220n c91 220n c113 270p 100v 0603 cx4 220n c75 20p 0805 j31 b2s 1 2 d37 dfls1200 jlch4 bnc 1 2 jch3 bnc 1 2 220n c97 jlch3 bnc 1 2 d31 dfls1200 220n cx12 d38 dfls1200 b2s j16 1 2 jlch2 bnc 1 2 b2s j15 1 2 c92 20p 0805 c87 220n d36 dfls1200 j28 b2s 1 2 d35 dfls1200 j25 con3 1 2 3 c86 220n r59 100k j20 b2s 1 2 cx8 220n r58 10k d32 dfls1200 c89 220n cx5 220n cx7 220n cx1 220n c77 r53 100 270p 100v 0603 jlch1 bnc 1 2 jch1 bnc 1 2 b2s j14 1 2 c112 270p 100v 0603 cx6 220n c102 220n c101 220n jch2 bnc 1 2 c74 20p 0805 220n c95 j21 b2s 1 2 220n cx9 j24 con3 1 2 3 c88 220n jch4 bnc 1 2 gspg30072014di1245
docid026791 rev 1 15/19 STEVAL-IME008V1 schematic diagrams 19 figure 14. STEVAL-IME008V1 circuit schematic (14 of 16) optional fpga i/o optional fpga configuration signals fpga_gpio0 fpga_gpio1 fpga_gpio2 fpga_gpio3 fpga_gpio4 fpga_gpio5 fpga_gpio6 fpga_gpio7 stm32_gpio_0 stm32_gpio_1 stm32_gpio_2 stm32_gpio_3 stm32_gpio_4 stm32_gpio_5 stm32_gpio_6 stm32_gpio_7 fpga_gpio[0:7] stm32_gpio_8 stm32_gpio_9 stm32_gpio_10 stm32_gpio_11 stm32_gpio_12 fpga_mcu_awake fpga_mcu_done mcu_fpga_osc_en mcu_fpga_init_b mcu_fpga_mode1 mcu_fpga_prog mcu_fpga_suspend stm32_gpio_13 stm32_gpio_14 fpga_gpio[0:7] fpga_mcu_awake fpga_mcu_done mcu_fpga_osc_en mcu_fpga_init_b mcu_fpga_mode1 mcu_fpga_prog mcu_fpga_suspend r80 0r - n/a r75 0r - n/a r74 0r - n/a r73 0r - n/a r89 0r - n/a r72 0r - n/a r88 0r - n/a r71 0r - n/a r70 0r - n/a r86 0r - n/a r69 0r - n/a r85 0r - n/a r84 0r - n/a r83 0r - n/a r82 0r - n/a jtag/swd male connector 2x5 pitch 1.27 mm samtec ftsh-105-01-f-d-k mcu jtag jntrst jtdo jtms jtdi jtck reset# mcu_3v3 mcu_3v3 r79 10k r77 10k 1 jp1 jumper 2 r76 10k r78 10k r87 10k j40 1 2 swd/jtag 3 4 5 6 7 8 9 10 gspg30072014di1250
schematic diagrams STEVAL-IME008V1 16/19 docid026791 rev 1 figure 15. STEVAL-IME008V1 circuit schematic (15 of 16) mcu place near mcu spi flash int spi flash flash disable c123 details: digikey (445-4998-2-nd) - tdk (c1005x5r0j105k) package 0402 use j38 to enable/disable power for spi flash device. j38 must be open when using external spi flash device on connecto j10. default value closed. stm32f103 user_led1 user_led2 boot0 boot1 oscin flash_ns flash_c flash_dq1 flash_dq0 jtms jtck jtdi jtdo jntrst reset# oscout flash_dq0 flash_dq1 stm32_gpio_10 stm32_gpio_11 stm32_gpio_12 stm32_gpio_13 stm32_gpio_14 stm32_gpio_0 stm32_gpio_1 stm32_gpio_2 stm32_gpio_3 stm32_gpio_4 stm32_gpio_5 stm32_gpio_6 stm32_gpio_7 stm32_gpio_8 stm32_gpio_9 vdda mcu_3v3 usb_disconnect dm_stm32 dp_stm32 flash_3v3 flash_dq2 flash_dq3 flash_c flash_ns flash_dq2 flash_dq3 flash_c flash_dq0 flash_ns flash_dq2 flash_dq3 flash_dq1 usb_disconnect usb_dm usb_dp mcu_3v3 flash_3v3 mcu_3v3 mcu_3v3 flash_3v3 mcu_3v3 j38 2 1 r66 4k7 d30 red c116 100nf 56 r128 c123 1uf 6.3v u10 1 vbat stm32f103c8t6 2 3 pc14-osc32_in pc15-osc32_out pc13-tamper-rtc 4 5 pd0 osc_in 6 pd1 osc_out 7 nrst 8 vssa 9 vdda 10 pa0-wkup pa1 11 pa2 12 pa3 13 pa4 14 pa5 15 pa6 16 pa7 17 pb0 18 pb1 19 20 pb2-boot1 pb10 21 pb11 22 vss_1 23 vdd_1 24 pb12 25 pb13 26 pb14 27 pb15 28 pa8 29 pa9 30 pa10 31 pa11 32 pa12 33 34 pa13 jtms vss_2 35 36 vdd_2 pa14 jtck pa15 jtdi 37 pb3 jtdo 38 pb4 jntrst 39 40 pb5 41 pb6 42 pb7 43 44 boot0 pb8 45 pb9 46 vss_3 47 vdd_3 48 c122 100nf u9 vcc 8 n25q032xsc 5 dq0 vss 4 c 6 ns 1 3 nw/vpp/dq2 7 nhold/dq3 dq1 2 r131 4k7 c121 100nf r64 0r - n/a c118 100nf r130 4k7 c119 100nf r129 4k7 c120 100nf r67 4k7 gspg30072014di1255
docid026791 rev 1 17/19 STEVAL-IME008V1 schematic diagrams 19 figure 16. STEVAL-IME008V1 circuit schematic (16 of 16) not assembly rs (505-9186) c&k (y78b22110fp) red kingbright kp2012surc rs: 466-3829 farnell: 8529930 led 0805 red kingbright kp2012surc rs: 466-3829 farnell: 8529930 led 0805 oscillator murata (cstce8m00g55-r0) digikey (490-1195-1-nd) rs: 283-961 farnell: 1615352 mcu reset 8mhz osc download flash ready reset# user_led1 user_led2 oscout oscin mcu_3v3 rst2 sw pushbutton-dpst d24 y1 8mhz r81 56r d25 r68 56r r65 10k c117 100nf gspg30072014di1300
revision history STEVAL-IME008V1 18/19 docid026791 rev 1 2 revision history table 1. document revision history date revision changes 06-aug-2014 1 initial release.
docid026791 rev 1 19/19 STEVAL-IME008V1 19 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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